pitlane/main.c

changeset 69
27c0c0095e26
parent 68
c3460121ad8b
child 70
3a57b7a70683
--- a/pitlane/main.c	Sat Dec 10 10:51:24 2011 +0100
+++ b/pitlane/main.c	Sat Dec 10 14:12:09 2011 +0100
@@ -94,7 +94,6 @@
     uint8_t enable = DDR(RESPONSE_PORT) | _BV(RESPONSE_PIN);
     uint8_t disable = DDR(RESPONSE_PORT) & ~_BV(RESPONSE_PIN);
     data |= 0b100000000000001; // make sure start/stop bits are set
-    data = 0b1010101010101011;
     while (index != 0) {
         if ((data & 1) != 0) {
             DDR(RESPONSE_PORT) = enable; // enable response output
@@ -348,9 +347,9 @@
                 // set inside status
                 for (tmp=0; tmp<MAX_SLOTS; tmp++)
                     if (slot[tmp].inside) {
-                    response = (1 | ((tmp)<<1) | (4 << 4));
                     slot[tmp].inside = 0;
                 }
+                response = (1 | (0b111 <<1) | (4 << 4));
                 RS232_puts_p(PSTR("PIT:EXIT\n"));
         }
 

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